6  Exception and Interrupt Processing

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6.1  Hardware Exception Sources

Handler StartException
0x80000100System Reset Interrupt
0x80000200Machine Check Interrupt
0x80000300DSI Interrupt
0x80000400ISI Interrupt
0x80000500External Interrupt
0x80000600Alignment Interrupt
0x80000700Program Interrupt
0x80000800FP unavailable Interrupt
0x80000900Decrementer Interrupt
0x80000C00System Call Interrupt
0x80000d00Trace Interrupt
0x80000f00Performance Monitor Interrupt
0x80001300IABR Interrupt
0x80001700Thermal Interrupt
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6.1.1  System Reset Interrupt

Triggered at a system reset
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6.1.2  Machine Check Interrupt

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6.1.3  DSI Interrupt

Triggered if an attempt to store or read data from/to an illegal address was made
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6.1.4  ISI Interrupt

Triggered if an attempt to fetch an instruction from an illegal address was made.
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6.1.5  External Interrupt

14 sources, triggered by external chips (you may look at it as the traditional IRQ).
6.1.5.1   Setup  
6.1.5.2   Handling  
bit Description
13HSPHigh Speed Port
12DEBUGExternal Debugger
11CPCommand FIFO
10PE FINISHFrame is Ready
9PE TOKENToken Assertion in Command List
8VI Video Interface
7MEMMemory Interface
6DSPDSP
5AIAudio Streaming
4EXIEXI
3SISerial
2DIDVD
1RSWReset Switch
0ERRORGP runtime error
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6.1.6  Alignment Interrupt

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6.1.7  Program Interrupt

Triggered if the instruction that was about to execute is invalid.
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6.1.8  FP unavailable Interrupt

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6.1.9  Decrementer Interrupt

Triggered by an underflow of the decrementer register.
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6.1.10  System Call Interrupt

Triggered when the PowerPC instruction 'sc' is executed.
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6.1.11  Trace Interrupt

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6.1.12  Performance Monitor Interrupt

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6.1.13  IABR Interrupt

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6.1.14  Thermal Interrupt

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6.2  External Interrupt Sources

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6.2.1  HSP - High Speed Port

3 Sources
6.2.1.1   TX Mailbox Interrupt  
6.2.1.2   RX Mailbox Interrupt  
6.2.1.3   ID Interrupt  
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6.2.2  Debug

1 Source
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6.2.3  CP - Command Processor

2 Sources (read/write pointer watermark over- and underflow) check bit 0 and bit 1 of 0xcc000000
6.2.3.1   FIFO underflow  

    6.2.3.1.1  setup  

    6.2.3.1.2  handling  
6.2.3.2   FIFO overflow  

    6.2.3.2.1  setup  

    6.2.3.2.2  handling  
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6.2.4  PE - Pixel Engine Finished

1 Source (Frame finished)
6.2.4.1   setup  
6.2.4.2   handling  
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6.2.5  PE - Pixel Engine Token

1 Source (Token in GP Command List)
6.2.5.1   setup  
6.2.5.2   handling  
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6.2.6  VI - Video Interface

4 Sources, check (0xcc002030) (0xcc002034) (0xcc002038) (0xcc00203c) for flags
6.2.6.1   Setup  
6.2.6.2   Handling  
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6.2.7  Memory Interface

4 sources (4 regions of memory can be protected independently)
6.2.7.1   protection fault  

    6.2.7.1.1  Setup  

    6.2.7.1.2  Handling  
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6.2.8  DSP Interface

3 Sources, check (0xcc00500a) for flags
6.2.8.1   Audio DMA finished  
asserted when audio DMA transfer has been completed.

    6.2.8.1.1  Setup  

    6.2.8.1.2  Handling  
6.2.8.2   ARAM transfer complete  
asserted when a transfer from/to auxiliary ram has been completed.
6.2.8.3   DSP  
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6.2.9  Audio Streaming Interface

1 Source, check (0xcc006c00) for flag. asserted based on the disk streaming sample counter.
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6.2.10  EXI

3 Sources each EXI Channel (TCINT,EXTINT,EXIIRQ), making 9 total, check (0xcc006800) (0xcc006814) (0xcc006828) for flags.
6.2.10.1   DMA Transfer finished (TCINT channel 0, channel 1)  
6.2.10.2   Ethernet Packet received (EXIIRQ channel 2)  
6.2.10.3   Memory Card removed (EXTINT channel 0, channel 1)  

    6.2.10.3.1  setup  

    6.2.10.3.2  handling  
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6.2.11  Serial Interface

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6.2.12  DVD Interface

4 Sources (Break Complete, DMA finished, Device Error, Cover state changed), check (0xcc006000)(0xcc006004) for flags.
6.2.12.1   Break Complete  
6.2.12.2   DMA finished  
6.2.12.3   Device Error  
6.2.12.4   Cover State changed  
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6.2.13  Reset Button

1 Source (Reset Button pressed)
6.2.13.1   setup  
6.2.13.2   handling  
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6.2.14  Error

1 Source (GP runtime error)
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